View MT89L80_2037944.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2-3 features ? 3.3 volt supply ? 5v tolerant inputs and ttl compatible outputs. ? 256 x 256 channel non-blocking switch ? accepts serial streams at 2.048mb/s ? per-channel three-state control ? patented per channel message mode ? non-multiplexed microprocessor interface ? mitel st-bus compatible ? low power consumption: typical 15mw ? pin compatible with the mt8980dp applications ? key telephone systems ? pbx systems ? small and medium voice switching systems description this vlsi cmos device is designed for switching pcm-encoded voice or data, under microprocessor control, in a modern digital exchange, pbx or central office. it provides simultaneous connections for up to 256 64 kbit/s channels. each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s st-bus stream. in addition, the MT89L80 provides microprocessor read and write access to individual st-bus channels. figure 1 - functional block diagram sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 serial to parallel converter data memory frame counter control register control interface output mux connection memory parallel to serial converter cs r/ w a5/ a0 dta d7/ d0 csto c4i f0i v dd v ss ** ode sti0 sti1 sti2 sti3 sti4 sti5 sti6 sti7 ds reset ** for 48-pin ssop only ds5196 issue 3 july 2002 MT89L80 digitalswitch cmos st-bus ? family ordering information MT89L80ap 44 pin plcc MT89L80an 48 pin ssop -40 c to +85 c advance information
MT89L80 advance information 2-4 figure 2 - pin connections pin description pin # name description 44 plcc 48 ssop 2 2 dta data acknowledgment (5v tolerant three-state output) . this active low output indicates that a data bus transfer is complete. a pull-up resistor is required at this output. 3-5 3-5 sti0-2 st-bus inputs 0 to 2 (5v-tolerant inputs). serial data input streams. these streams have data rates of 2.048mbit/s with 32 channels. 7-11 7-11 sti3-7 st-bus inputs 3 to 7 (5v-tolerant inputs). serial data input streams. these streams may have data rates of 2.048mbit/s with 32channels. 12 12,36 v dd +3.3 volt power supply . 13 reset device reset ( 5v-tolerant input). this pin is only available for the 48-pin ssop package.this active low input puts the device in its reset state. it clears the internal counters and registers. all st-bus outputs are set to the high impedance state. in normal operation. the reset pin must be held low for a minimum of 100nsec to reset the device. internal pull-up. 13 14 f0i frame pulse (5v-tolerant input). this is the input for the frame synchronization pulse for the 2048 kbit/s st-bus streams. a low on this input causes the internal counter to reset on the next negative transition of c4i . 14 15 c4i 4.096 mhz clock (5v-tolerant input). st-bus bit cell boundaries lie on the alternate falling edges of this clock. 15-17 16-18 a0-2 address 0-2 / input streams 8-10 (5v-tolerant input). these are the inputs for the address lines on the microprocessor interface. 1 6 5 4 3 2 4 4 4 3 4 2 4 1 4 0 7 8 9 10 11 12 13 14 15 16 39 38 37 36 35 34 33 32 31 30 2 3 1 8 1 9 2 0 2 1 2 2 2 4 2 5 2 6 2 7 2 8 17 29 sti3 sti4 sti5 sti6 sti7 v dd f0i c4i a0 a1 a2 sto3 sto4 sto5 sto6 sto7 v ss d0 d1 d2 d3 d4 n c s t i 1 d t a o d e s t o 1 n c n c a 4 d s c s d 6 n c a 3 a 5 r / w d 7 d 5 44 pin plcc s t i 2 s t i 0 c s t o s t o 0 s t o 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 48 pin ssop 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 ode sto0 sto1 sto2 nc sto3 sto4 sto5 sto6 sto7 v ss v dd d0 d1 d2 d3 d4 nc d5 d6 dta sti0 sti1 sti2 nc sti3 sti4 sti5 sti6 sti7 v dd reset f0i c4i a0 a1 a2 nc a3 a4 48 csto v ss 21 27 d7 a5 22 26 cs ds 23 25 v ss r/ w 24 (jedec mo-118, 300mil wide)
advance information MT89L80 2-5 19-21 20-22 a3-5 address 3-5 / input streams 11-13 (5v-tolerant input). these are the inputs for the address lines on the microprocessor interface. 22 23 ds data strobe (5v-tolerant input). this is the input for the active high data strobe on the microprocessor interface. 23 24 r/ w read/write (5v-tolerant input). this is the input for the read/write signal on the microprocessor interface - high for read, low for write. 24 26 cs chip select (5v-tolerant input). this is the input for the active low chip select on the microprocessor interface 25-27 27-29 d7-d5 data bus (5v-tolerant i/o): these are the bidirectional data pins on the microprocessor interface. 29-33 31-35 d4-d0 data bus (5v-tolerant i/o): these are the bidirectional data pins on the microprocessor interface. 34 1, 25,37 v ss ground . 35-39 38-42 sto7-3 st-bus outputs 7 to 3 (5v-tolerant three-state outputs). these are the pins for the eight 2048 kbit/s st-bus output streams. 41-43 44-46 sto2-0 st-bus outputs 2to 0 (5v-tolerant three-state outputs). these are the pins for the eight 2048kbit/s st-bus output streams. 44 47 ode output drive enable (5v-tolerant input). if this input is held high, the sto0-sto7 output drivers function normally. if this input is low, the sto0-sto7 output drivers go into their high impedance state. nb: even when ode is high, channels on the sto0- sto7 outputs can go high impedance under software control. 1 48 csto control st-bus output (5v-tolerant output). each frame of 256 bits on this st-bus output contains the values of bit 1 in the 256 locations of the connection memory high. 6, 18, 28, 40 6, 19, 30, 43 nc no connection . pin description (continued) pin # name description 44 plcc 48 ssop
MT89L80 advance information 2-6 functional description in recent years, there has been a trend in telephony towards digital switching, particularly in association with software control. simultaneously, there has been a trend in system architectures towards distributed processing or multi-processor systems. in accordance with these trends, mitel has devised the st-bus (serial telecom bus). this bus architecture can be used both in software-controlled digital voice and data switching, and for interprocessor communications. the uses in switching and in interprocessor communications are completely integrated to allow for a simple general purpose architecture appropriate for the systems of the future. the serial streams of the st-bus operate continuously at 2048 kbit/s and are arranged in 125 m s wide frames which contain 32 8-bit channels. mitel manufactures a number of devices which interface to the st-bus; a key device being the MT89L80 chip. the MT89L80 can switch data from channels on st- bus inputs to channels on st-bus outputs, and simultaneously allows its controlling microprocessor to read channels on st-bus inputs or write to channels on st-bus outputs (message mode). to the microprocessor, the MT89L80 looks like a memory peripheral. the microprocessor can write to the MT89L80 to establish switched connections between input st-bus channels and output st-bus channels, or to transmit messages on output st- bus channels. by reading from the MT89L80, the microprocessor can receive messages from st-bus input channels or check which switched connections have already been established. by integrating both switching and interprocessor communications, the MT89L80 allows systems to use distributed processing and to switch voice or data in an st-bus architecture. hardware description serial data at 2048 kbit/s is received at the eight st- bus inputs (sti0 to sti7), and serial data is transmitted at the eight st-bus outputs (sto0 to sto7). each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a pcm-encoded analog/voice sample as provided by a codec (e.g., mitel?s mt8964). this serial input word is converted into parallel data and stored in the 256 x 8 data memory. locations in the data memory are associated with particular channels on particular st-bus input streams. these locations can be read by the microprocessor which controls the chip. locations in the connection memory, which is split into high and low parts, are associated with particular st-bus output streams. when a channel is due to be transmitted on an st-bus output, the data for the channel can either be switched from an st-bus input or it can originate from the microprocessor. if the data is switched from an input, then the contents of the connection memory low location associated with the output channel is used to address the data memory. this data memory address corresponds to the channel on the input st-bus stream on which the data for switching arrived. if the data for the output channel originates from the microprocessor (message mode), then the contents of the connection memory low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes. the connection memory data is received, via the control interface, at d7 to d0. the control interface also receives address information at a5 to a0 and handles the microprocessor control signals cs , dta , r/ w and ds. there are two parts to any address in the data memory or connection memory. figure 3- address memory map a5 a4 a3 a2 a1 a0 hex address location 0 1 1 ? ? ? 1 0 0 0 ? ? ? 1 0 0 0 ? ? ? 1 0 0 0 ? ? ? 1 0 0 0 ? ? ? 1 0 0 1 ? ? ? 1 00 - 1f 20 21 ? ? ? 3f control register * channel 0 ? channel 1 ? ? ? ? channel 31 ? * writing to the control register is the only fast transaction. ? memory and stream are specified by the contents of the control register.
advance information MT89L80 2-7 the higher order bits come from the control register, which may be written to or read from via the control interface. the lower order bits come from the address lines directly. the control register also allows the chip to broadcast messages on all st-bus outputs (i.e., to put every channel into message mode), or to split the memory so that reads are from the data memory and writes are to the connection memory low. the connection memory high determines whether individual output channels are in message mode, and allows individual output channels to go into a high-impedance state, which enables arrays of MT89L80s to be constructed. it also controls the csto pin. all st-bus timing is derived from the two signals c4i and f0i . software control the address lines on the control interface give access to the control register directly or, depending on the contents of the control register, to the high or low sections of the connection memory or to the data memory. if address line a5 is low, then the control register is addressed regardless of the other address lines (see fig. 3). if a5 is high, then the address lines a4-a0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the control register. the data in the control register consists of mode control bits, memory select bits, and stream address bits (see fig. 4). the memory select bits allow the connection memory high or low or the data memory to be chosen, and the stream address bits define one of the st-bus input or output streams. bit 7 of the control register allows split memory operation - reads are from the data memory and writes are to the connection memory low. the other mode control bit, bit 6, puts every output channel on every output stream into active message mode; i.e., the contents of the connection memory low are output on the st-bus output streams once every frame unless the ode pin is low. in this mode the chip behaves as if bits 2 and 0 of every connection memory high location were 1, regardless of the actual values. figure 4 - control register bits bit name description 7 split memory when 1, all subsequent reads are from the data memory and writes are to the connection memory low, except when the control register is accessed again. when 0, the memory select bits specify the memory for subsequent operations. in either case, the stream address bits select the subsection of the memory which is made available. 6 message mode when 1, the contents of the connection memory low are output on the serial output streams except when the ode pin is low. when 0, the connection memory bits for each channel determine what is output. 5 (unused) 4-3 memory select bits 0-0 - not to be used 0-1 - data memory (read only from the microprocessor port) 1-0 - connection memory low 1-1 - connection memory high 2-0 stream address bits the number expressed in binary notation on these bits refers to the input or output st- bus stream which corresponds to the subsection of memory made accessible for subsequent operations. 7 6 5 4 3 2 1 0 mode control bits (unused) memory select bits stream address bits
MT89L80 advance information 2-8 figure 5 - connection memory high bits figure 6 - connection memory low bits bit namee description 2 message channel when 1, the contents of the corresponding location in connection memory low are output on the location?s channel and stream. when 0, the contents of the corresponding location in connection memory low act as an address for the data memory and so determine the source of the connection to the location?s channel and stream. 1 csto bit this bit is output on the csto pin one channel early. the csto bit for stream 0 is output first. 0 output enable if the ode pin is high and bit 6 of the control register is 0, then this bit enables the output driver for the location?s channel and stream. this allows individual channels on individual streams to be made high-impedance, allowing switching matrices to be constructed. a 1 enables the driver and a 0 disables it. bit name description 7-5* stream address bits* the number expressed in binary notation on these 3 bits is the number of the st-bus stream for the source of the connection. bit 7 is the most significant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on sti4. 4-0* channel address bits* the number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (the st-bus stream where the channel lies is defined by bits 7, 6 and 5.). bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19. *if bit 2 of the corresponding connection high location is 1 or if bit 6 of the control register is 1, then these entire 8 bits are output on the channel and stream associated with this location. otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. 7 6 5 4 3 2 1 0 no corresponding memory - these bits give 0s if read. per channel control bits 7 6 5 4 3 2 1 0 stream address bits channel address bits
advance information MT89L80 2-9 if bit 6 of the control register is 0, then bits 2 and 0 of each connection memory high location function normally (see fig. 5). if bit 2 is 1, the associated st- bus output channel is in message mode; i.e., the byte in the corresponding connection memory low location is transmitted on the stream at that channel. otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the connection memory low define the st-bus input stream and channel where the byte is to be found (see fig. 6). if the ode pin is low, then all serial outputs are high- impedance. if it is high and bit 6 in the control register is 1, then all outputs are active. if the ode pin is high and bit 6 in the control register is 0, then the bit 0 in the connection memory high location enables the output drivers for the corresponding individual st-bus output stream and channel. bit 0=1 enables the driver and bit 0=0 disables it (see fig. 5). bit 1 of each connection memory high location (see fig. 5) is output on the csto pin once every frame. to allow for delay in any external control circuitry the bit is output one channel before the corresponding channel on the st-bus streams, and the bit for stream 0 is output first in the channel; e.g., bit 1?s for channel 9 of streams 0-7 are output synchronously with st-bus channel 8 bits 7-0. applications use in a simple digital switching system figs. 7 and 8 show how MT89L80s can be used with mt8964s to form a simple digital switching system. fig. 7 shows the interface between the MT89L80s and the filter/codecs. fig. 8 shows the position of these components in an example architecture. the mt8964 filter/codec in fig. 7 receives and transmits digitized voice signals on the st-bus input d r , and st-bus output d x , respectively. these signals are routed to the st-bus inputs and outputs on the top MT89L80, which is used as a digital speech switch. the mt8964 is controlled by the st-bus input d c originating from the bottom MT89L80, which generates the appropriate signals from an output channel in message mode. this architecture optimizes the messaging capability of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an st-bus output. this signalling st-bus output is monitored by a microprocessor (not shown) through an st-bus input on the bottom MT89L80. fig. 8 shows how a simple digital switching system may be designed using the st-bus architecture. this is a private telephone network with 256 extensions which uses a single MT89L80 as a speech switch and a second MT89L80 for communication with the line interface circuits. figure 7 - example of typical interface between 89l80s and 8964s for simple digital switching system 89l80 used as speech switch MT89L80 sto0 sti0 sto0 sti0 MT89L80 89l80 used in message mode for control and signalling d x d r d c mt8964 filter/codec signalling logic line driver and 2- to 4- wire converter line interface circuit with 8964 filter/codec
MT89L80 advance information 2-10 figure 8 - example architecture of a simple digital switching system controlling micro- processor speech switch - 89l80 control & signalling - 89l80 sto0-7 sti0-7 sto0-7 line interface circuit with codec (e.g. 8964) line 1 line 256 line interface circuit with codec (e.g.8964) 8 8 8 8 ? ? ? repeated for lines 2 to 255 ? ? ? repeated for lines 2 to 255 sti0-7
advance information MT89L80 2-11 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. . ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * absolute maximum ratings* parameter symbol min max units 1 supply voltage -0.3 5.0 v 2 voltage on any i/o pin (except supply pins) v o v ss -0.3 v dd +0.3 v 3 current at digital outputs i o 20 ma 4 storage temperature t s -55 +125 c 5 package power dissipation p d 1 w recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ max units test conditions 1 operating temperature t op -40 +85 c 2 positive supply v dd 3.0 3.6 v 3 input high voltage v ih 0.7v dd v dd v 4 input high voltage on 5v tolerant inputs v ih 5.5 v 5 input low voltage v il v ss 0.3v dd v dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 i n p u t s supply current i dd 4 7 ma outputs unloaded 2 input high voltage v ih 0.7v dd v 3 input low voltage v il 0.3v dd v 4 input leakage i il 5 m a v i between v ss and v dd 5 input pin capacitance c i 10 pf 6 o u t p u t s output high voltage v oh 0.8v dd v i oh = 10 ma 7 output high current i oh 10 ma sourcing. v oh =2.4v 8 output low voltage v ol 0.4 v i ol = 5 ma 9 output low current i ol 5 ma sinking. v ol = 0.4v 10 high impedance leakage i oz 5 m a v o between v ss and v dd 11 output pin capacitance c o 10 pf ac electrical characteristics _ timing parameter measurement voltage levels characteristics sym level units test conditions 1 cmos threshold voltage v tt 0.5v dd v 2 cmos rise/fall threshold voltage high v hm 0.7v dd v 3 cmos rise/fall threshold voltage low v lm 0.3v dd v
MT89L80 advance information 2-12 ? timing is over recommended temperature & power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * contents of connection memory are not lost if the clock stops, however, st-bus outputs go into the high impedance state. nb: frame pulse is repeated every 512 cycles of c4i . figure 9- frame alignment figure 10 - clock timing ac electrical characteristics ? - clock timing (figures 9 and 10) characteristics sym min typ ? max units test conditions 1 i n p u t s clock period* t clk 220 244 300 ns 2 clock width high t ch 85 122 150 ns 3 clock width low t cl 85 122 150 ns 4 clock transition time t ctt 10 ns 5 frame pulse setuptime t fps 10 190 ns 6 frame pulse hold time t fph 10 190 ns 7 frame pulse width t fpw 244 ns c4i f0i bit cells channel 31 bit o channel 0 bit 7 t clk t ctt t ch t chl t ctt t fph t fps t fph t fps t fpw t cl c4i f0i v hm v lm v hm v lm
advance information MT89L80 2-13 ? timing is over recommended temperature & power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . ac electrical characteristics ? - serial streams (figures 11, 12 and 13) characteristics sym min typ ? max units test conditions 1 o u t p u t s sto0/7 delay - active to high z t saz 5 55 ns r l =1 k w * , c l =150 pf 2 sto0/7 delay - high z to active t sza 5 55 ns c l =150 pf 3 sto0/7 delay - active to active t saa 5 55 ns c l =150 pf 4 output driver enable delay t oed 50 ns r l =1 k w * , c l =150 pf 5 external control delay t xcd 55 ns c l =150 pf 6 i n serial input setup time t sis 20 ns 7 serial input hold time t sih 20 ns figure 11 - serial outputs and external control figure 12 - output driver enable figure 13 - serial inputs c4i sto0 to sto7 sto0 to sto7 sto0 to csto bit cell boundary sto7 t saz t sza t saa t xcd * * v hm v lm v hm v lm v hm v lm v hm v lm v hm v lm ode sto0 to sto7 * t oed t oed * v hm v lm v hm v lm bit cell boundaries c4i sti0 to sti7 t sis t sih v hm v lm v hm v lm
MT89L80 advance information 2-14 ? timing is over recommended temperature & power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . figure 14 - processor bus ac electrical characteristics ? - processor bus (figures 14) characteristics sym min typ ? max units test conditions 1 chip select setup time t css 0 ns 2 read/write setup time t rws 5 ns 3 address setup time t ads 5 ns 4 acknowledgment delay control register read t akd 52 120 ns c l =150 pf control register write t akd 25 65 ns c l =150 pf connection memory read t akd 62 120 ns c l =150 pf connection memory write t akd 30 53 ns c l =150 pf data memory read t akd 560 1220 ns c l =150 pf 5 fast write data setup time t fws 0 ns 6 slow write data delay t swd 122 ns 7 read data setup time t rds 0 ns c l = 150 pf 8 data hold time read write t dht 10 90 ns r l =1 k w * , c l =150 pf t dht 5 10 ns 9 read data to high impedance t rdz 15 50 90 ns r l =1 k w * , c l =150 pf 10 chip select hold time t csh 0 ns 11 read/write hold time t rwh 0 ns 12 address hold time t adh 8 ns 13 acknowledgment hold time t akh 50 80 ns r l =1 k w * , c l =150 pf ds cs r/ w a5 to a0 dta d7 to d0 t css t rws t ads t akd t rds t swd t fws t csh t rwh t adh t akh t dht * * * * t rdz v hm v lm v hm v lm v hm v lm v hm v lm v hm v lm v hm v lm

c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

▲Up To Search▲

Price & Availability of MT89L80

	To Download MT89L80 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .